module ALU(clk, reset, ALUcontrolOut, data1, data2, ifZero, ALUresult);
    input wire clk;
    input wire reset;
    input wire[3:0] ALUcontrolOut;
    input wire[31:0] data1, data2;
    output reg ifZero;
    output reg[31:0] ALUresult;

    parameter addOP = 4'b0010;
    parameter subOP = 4'b0110;
    parameter andOP = 4'b0000;
    parameter orOP  = 4'b0001;
    parameter errorOP = 4'b1111;

    // always @(posedge reset)
    // begin
    //     ifZero = 0;
    //     ALUresult = 32'hffff;
    // end

    always @(ALUcontrolOut, data1, data2)
    begin
        case(ALUcontrolOut)
            addOP : ALUresult = data1 + data2;
            subOP : ALUresult = data1 - data2;
            andOP : ALUresult = data1 & data2;
            orOP : ALUresult = data1 | data2;
            default : ALUresult = 32'hffffffff;
        endcase
        if(ALUresult == 0) ifZero = 1;
    end


endmodule